A Hybrid Power Modeling Approach To Improve High-Level Power Characterization

Power consumption is the one key concern in today digital design flow. Optimization techniques are applied at early stages to reduce the power consumed by the chip. Accurate and efficient power models at high abstraction levels are needed, as it is at this stage when most of the power saving is accomplished. High-level power models are constructed with pre-characterized power values based on estimation techniques at different abstraction levels. The most accurate results are obtained at low-abstraction levels, as the complete circuit structure is well known. However, the simulation runtime is prohibitive to analyze complex circuits. Thus, characterization points based on low-level simulation without runtime drawback are desired. In this work, we proposed a hybrid power modeling approach that takes into account power-related information from different abstraction levels. The major purpose of our approach is to enhance highlevel power models by having a fast analysis with a transistorlike accuracy. Our approach is composed of b two main phases, a library characterization methodology, and an efficient power estimation flow. As test case, we perform experiments on benchmark circuits synthesized with a 28nm “Fully Depleted Silicon on Insulator” (FDSOI) technology. We compare our results with transistor simulations results and show that we can achieve an accuracy close to 6% with a runtime speedup close to 60X.